As computers become increasingly complex, the need for memory storage, and in particular memory cells, increases. At the same time, there is the need to minimize the size of computers. Moreover, with advent of laptop computers and other devices requiring low power usage, the amount of power consumed by a memory cell becomes critical, as the power consumed by a memory cell affects the length of time between recharging of the batteries used with same. In order to optimize both needs, the memory cells of the computer must, by necessity, be made smaller and more energy efficient.
A memory cell stores one bit of information. Bits are commonly represented by the binary digits 0 and 1. A single computer can store millions or even billions of bits.
A conventional non-volatile semiconductor memory device in which contents are electrically programmable and simultaneously erased by one operation (hereinafter called "flash memory") includes a plurality of memory cells each provided with a floating gate covered with an insulating layer. There is also a control gate which overlays the insulating layer. The insulating layer is often termed the interpoly oxide layer. Below the floating gate is another insulating layer sandwiched between the floating gate and the substrate. The substrate contains the doped source and drain regions. A channel region is disposed between the source and drain regions.
In flash memory, a charged floating gate is one logic state, typically represented by the binary digit 1, while a non-charged floating gate is the opposite logic state typically represented by the binary digit 0. Charges are injected or written to a floating gate by any number of methods, including avalanche injection, channel injection, Fowler-Nordheim tunneling, and channel hot electron injection, for example. The floating gate is discharged or erased by any number of methods including Fowler-Nordheim tunneling, for example.
During the write operation, the control gate is set at a high voltage, 12 volts, for example. The drain is also set at a high voltage usually around 6 volts. The source is kept at 0 volts or ground. With these voltage levels, electrons are trapped in the floating gate, thus leaving it in a charged state.
The erasing or discharging operation is typically accomplished by applying a relatively high voltage (approximately 12 volts) to the source of the cell while the gate is grounded, and the drain region is usually floating.
It is desired that the charging and discharging of the floating gate be accomplished by voltages lower than those used in the prior art. If lower voltages are used, then the power consumed by the charging and discharging of a memory cell is reduced.
One way to lower the voltages for writing and erasing is to increase the coupling between the control gate (also known as the wordline layer) and the floating gate. Coupling refers to the relationship between the voltage on the control gate and the voltage on the floating gate. The better the floating gate voltage coincides with the control gate voltage, the better the coupling.
For example, if a voltage V.sub.m is applied to the control gate, one obtains the voltage V.sub.f on the floating gate by calculating the coupling factor .gamma. which associates those two voltages according to the relation: V.sub.f =.gamma..times.V.sub.m. Therefore, an increase in the coupling factor .gamma. is an increase in coupling which in turn allows charging and discharging with lower voltages than a cell with a lower .gamma. coupling factor.
The coupling factor (.gamma.) is thus the ratio of capacitance between the floating gate and the control gate to the sum of the capacitance between the floating gate and the control gate plus all capacitances between the floating gate and the substrate. Therefore, it can be increased by reducing the capacitance between the floating gate and the substrate.
One prior art attempt at increasing the coupling has been to use rough polycrystalline silicon for the floating gate. However, this method, while effective, can cause undesirable processing difficulties. For example, as the size of memory cells have decreased, the use of rough polysilicon has had a propensity for occluding contact openings and causing other similar problems.
Another prior art solution to the coupling problem has been to use a CMP cell. While this structure has resulted in improved coupling efficiency, it is, however, a very complicated structure. Further, it is difficult to integrate with other peripheral devices.
Still further, as the geometries of memory cells have steadily decreased, designers and fabricators have sought after a means by which the capacitance and coupling efficiency of a memory cell could be easily increased, without correspondingly increasing the size of the memory cell.
A high density flash memory cell and method for forming a line of floating gate transistors is the subject matter of the present invention.